Author: Ted Obuchowicz Date: July 10, 2010 Modified: April 10, 2012 for use on Linux systems. By : Ted Obuchowicz - fixed the Warning: Cannot convert string "SunCopy" to type VirtualBinding- messages whicvh caused problems with Set Force in the GUI for Solaris 5.8 NOTE: When running Verilog-XL GUI version (graphical user interface) make sure that the UNIX environment variable XKEYSYMDB is NOT SET. (you can do unsetenv XKEYSYMDB from the UNIX prompt, also ensure it is not defined in your .cshrc or .login (or, if sh or ksh, .profile) If this variable is set, and if you try to do a Set Force on a signal in the GUI, you will not be able to select a value with the mouse... also many warning messages about Warning: Cannot convert string "SunCopy" to type VirtualBinding Warning: Cannot convert string "SunCut" to type VirtualBinding Warning: Cannot convert string "SunPaste" to type VirtualBinding Warning: translation table syntax error: Unknown keysym name: osfActivate Warning: ... found while parsing ':osfActivate:ManagerParentActivate() will be generated. unsetenving the XKEYSYMDB variable fixes the problem. No warnings are generated and the Set Force now is able to select a value for a signal with the mouse button. The /CMC/ENVIRONMENT/verilog.env file has been modified so that the line which sets XKEYSYMDB has been commented out. If you are sourcing other files either from the command line of automatically via .cshrc file, make sure that you unsetenv XKEYSYMDB begore running the graphical Verilog-XL simulator. Revised: -------- July 17, 2007: modified for running verilog_2006a found in /CMC/tools/cadence.2006a/IUS stream GUI commands are slightly different from 2004a version A simple guide to running Cadence's Verilog-XL compiler: ------------------------------------------------------ 1) setup the Linux environment to run Verilog-XL by typing the following from the UNIX prompt: source /CMC/ENVIRONMENT/verilog.env this command should execute without printing any output as in: ted@flash Example0 1:24pm >source /CMC/ENVIRONMENT/verilog.env ted@flash Example0 1:26pm > if anything is displayed on the screen when you issue this command, then something is amiss; send a mail to helpdesk@ece.concordia.ca describing the situation. 2) create a working directory to store your Verilog source code in: mkdir VERILOG 3) change into the directory you just created : cd VERILOG 4) use any UNIX ASCII text editor such as xedit, vi, emacs, etc. to create your Verilog source code. As an example, we will create two files which will specify a 2-input OR gate, and a testbench which will apply stimuli to the inputs of the testbench. The file or_gate.v should contain the following: module Verilog_or (out, a,b); input a,b; output out; reg out ; always @ (a or b ) begin out = a | b; end endmodule The file tester.v should contain the following: module tester; reg in_a, in_b; wire out; Verilog_or my_or_gate(out, in_a, in_b); initial begin $monitor("time = %0t, in_a = %b, in_b = %b, out = %b", $time, in_a, in_b, out ); #1 in_a = 1'b0; in_b = 1'b0; #1000 in_a = 1'b0; in_b = 1'b1; #1000 in_a = 1'b1; in_b = 1'b0; #1000 in_a = 1'b1; in_b = 1'b1; end endmodule Note, that by convention Verilog source code files have a .v filename extension. The next step will illustrate how to run the Verilog-XL compiler and simulator in COMMAND-LINE mode (i.e. no graphical simulation environment) 5) Compile your source code with the Verilog-XL compiler with the following command: verilog or_gate.v tester.v -s This command will invoke the Verilog-XL compiler to compile the specified source files and to then enter the interactive simulator mode (this is what the -s option means). You will then see displayed on your screen the following: (Note: the version numbers displayed may differ from those given in this document) Tool: VERILOG-XL 08.20.001-p Jul 7, 2010 12:29:11 Copyright (c) 1995-2004 Cadence Design Systems, Inc. All Rights Reserved. Unpublished -- rights reserved under the copyright laws of the United States. Copyright (c) 1995-2004 UNIX Systems Laboratories, Inc. Reproduced with Permission. THIS SOFTWARE AND ON-LINE DOCUMENTATION CONTAIN CONFIDENTIAL INFORMATION AND TRADE SECRETS OF CADENCE DESIGN SYSTEMS, INC. USE, DISCLOSURE, OR REPRODUCTION IS PROHIBITED WITHOUT THE PRIOR EXPRESS WRITTEN PERMISSION OF CADENCE DESIGN SYSTEMS, INC. RESTRICTED RIGHTS LEGEND Use, duplication, or disclosure by the Government is subject to restrictions as set forth in subparagraph (c)(1)(ii) of the Rights in Technical Data and Computer Software clause at DFARS 252.227-7013 or subparagraphs (c)(1) and (2) of Commercial Computer Software -- Restricted Rights at 48 CFR 52.227-19, as applicable. Cadence Design Systems, Inc. 555 River Oaks Parkway San Jose, California 95134 For technical assistance please contact the Cadence Response Center at 1-877-CDS-4911 or send email to support@cadence.com For more information on Cadence's Verilog-XL product line send email to talkv@cadence.com Compiling source file "or_gate.v" Compiling source file "tester.v" Highest level modules: tester Type ? for help C1 > PLEASE DO NOT SEND ANY SUPPORT QUESTIONS TO THE ABOVE STATED ADDRESS. SHOULD YOU ENCOUNTER PROBLEMS, SEND A WELL DOCUMENTED EMAIL MESSAGE TO helpdesk@ece.concordia.ca The C1> is the prompt for the command line simulator. It is waiting for you to enter simulation commands. Let us first specify that the simulation should stop after 4000 time units (this is necessary since the particular testbench contains an always block which will run forever if we don't set an explicit stop time!) C1 > #4000 $stop; (please note that it is a semicolon and not a colon after the stop) Note that know the prompt changes to C2 > We will use the . to continue the simulation: C2 > . time = 0, in_a = x, in_b = x, out = x time = 1, in_a = 0, in_b = 0, out = 0 time = 1001, in_a = 0, in_b = 1, out = 1 time = 2001, in_a = 1, in_b = 0, out = 1 time = 3001, in_a = 1, in_b = 1, out = 1 C1: $stop at simulation time 4000 C2 > note that the simulator prints out the values of the time and inputs and outputs to our OR gate. This was expressly written in the testbench. Now, we exit the simulation environment with the $finish; system call: C2 > $finish; C2: $finish at simulation time 4000 0 simulation events (use +profile or +listcounts option to count) CPU time: 0.3 secs to compile + 0.0 secs to link + 0.0 secs in simulation End of Tool: VERILOG-XL 08.20.001-p Jul 7, 2010 12:32:50 Next, we will quickly show how to use the graphical interface version: 6) recompile your or_gate.v with the +gui option and the -s option. The +gui option is used to invoke the Verilog graphical environment (we keep the -s option since we want to still enter the interactive mode, interactive means we supply simulation commands through the command line or the graphical interface) verilog or_gate.v +gui -s After some time (which may vary depending on the speed of your workstation), two windows will appear: Console - SimVision Design Browser 1 - SimVision You will see the C1 > prompt in the middle of the Console - SimVision window. In the Design Brwoser 1 - SimVision window you will see in the left hane pane: - simulator | |--- Verilog_or Using the left mouse button select the small icon next to the Verilog_or in the Design Browser window. The top-level ports of the module will now be listed in the Name pane of the Design Browser window: -> a -> b -> out Let us select some signals to be traced with the SimVision waveform viewer. Move the mouse over one of the ports in the Design Browser Name pane and RIGHT-CLICK and hold the right mouse button over a signal name. A pop-up menu will appear, scroll down to the "Send to Waveform window" (while keeping the right mouse button depressed) and then release the right mouse button over this choice. The SimVision Waveform window will appear with your selected signal. Repeat the above for the other signals you wish to view in the Waveform window. the main window the following: Next, we need to give some values to our two inputs. Right click on the input signal 'a' in the top part of the window, release the right mouse button over the "Create Force" item, in the Create Force window give a value of 0 to this signal by position the mouse cursor to the end of the Value string and delete the z value and replace it with a 0 value ( 1'b0 in the vernacular of Verilog means a 1 bit binary signal with value of 0). Click OK in the Create Force window. Repeat the above the set the second input to 0 as well. You will see in the console window the folowiong messages: C1 > force Verilog_or.a = 'b0; $shm_open("waves.shm"); C1 > $shm_probe(Verilog_or.a); force Verilog_or.a = 'b0; C2 > force Verilog_or.b = 'b0; C3 > >From the simulator prompt (the C > in the bottom portion of the window) , we will set a BREAKPOINT at time = 1000 units. #1000 $stop; to run the simulation until this breakpoint , enter a . from the simulator prompt in the command window: C6> . YOU WILL NOTE THAT IN THE WAVEFORM WINDOW THE OUTPUT IS SPECIFIED IN RED AND IS LABELLED AS X (unknown). THIS IS A KNOWN BUG IN THE TOOL. FOR SOME REASON, INITIALY SPECIFIED VALUES ARE IGNORED. next, use the Set Force to give values of 1 to both inputs, set a breakpoint at time equal to 2000 units with the #2000 $stop; command and click the big triangle. You can click on the View -> Zoom -> Full X button in the waveform window to expand the display . You will see that the output has value of 0. Next, set the inputs to 0, set a breakpoint at some specified time and run the simulator. The output will go to 0 this time. Exit the simulator with the $finish; command Exit the SimVision window by left clicking File ---> Exit and reconfirm your exit decision in the window which will appear. There are several sources of information one can refer to if more information is required: 1) Cadence online documentation. There are PDF files for the Cadence Verilog-XL compiler found in: /CMC/tools/cadence/IUS/doc/vloguser/vloguser.pdf /CMC/tools/cadence/IUS/doc/vlogref/vlogref.pdf You may view these using the 'acroread' command: acroread /CMC/tools/cadence/IUS/doc/vloguser/vloguser.pdf will open up the Adobe Acrobat PDF reader. 2) There are many textbooks on the Verilog language itself (they do not show how to use a particular tool) The Verilog Hardware Description Language, Third Edition by Thomas and Moorby Kluwer Academic Press ISBN 0-7923-9723-1 Verilog Digital System Design by Z. Navabi McGraw Hill ISBN 0-07-047164-9 are two detailed texts on the subject.