Theses Supervised

Completed Theses:

Doctoral.

· Seyed Ebrahim Esmaeili-(Ph.D. 2011), co-supervised with Dr. Glenn Cowan,

· "Power Reduction Techniques in Clock Distribution Networks with Emphasis

· on LC Resonant Clocking".

· Houman Zarrabi- (Ph.D. 2011), co-supervised with Dr. Yvon Savaria,

Thesis Title: “Multilayer Modeling and Design of Energy Managed Microsystems”

· Afshin Nourivand- (Ph.D. 2011),co-supervised with Dr. Yvon Savaria

Thesis Title: “Yield-Aware Leakage Power Reduction of On-Chip SRAMs”

· Haydar Saeid – (Ph.D. 2004), co-supervised with Dr. D. Al-Khalili.
Thesis Title: “Tuning and Topology Optimization of the Clock Distribution Network under Obstacle Constraints”.

· Adnan Kabbani (Ph.D. 2004), co-supervised with Dr. D. Al-Khalili 

Thesis Title: “Timing Driven IP Block Design Flow with Emphasis on Reuseability” 

· R.V. Pillai (Ph.D. 1999), co-supervised with Dr. D. AlKhalili

Thesis Title: “Low Power Floating-Point Architectures for DSP”.

· Shereef Shehata, (Ph.D. 1997), co-supervision with Dr. B. Haroun
Thesis Title: “High Level Synthesis of Digital Signal Processing”.

· Michael Esonu, (Ph.D. 1991), co-supervision with Dr. Hariri .

Thesis Title: “Performance Analysis and Design of Area Efficient Fault Tolarant Systolic Arrays”

· R. Dantu (Ph.D. 1990), co-supervision with Drs. R.V. Patel and N. Dimopolous.
Thesis Title: “A Computer Vision System for VLSI Wafer Probing”.

· Raad. Al-Ashoor (Ph.D. 1990), co-supervision with Dr. R. V. Patel.
Thesis Title: “Robust Adaptive Control of Robot Manipulators”.

Master of Applied Science.

· Ali Mohammadi Farhangi (M.A.Sc. 2011),

Thesis Title: “Congestion Driven Clock Tree Routing with Via Minimization”

· Jacques Athow (M.A.Sc. 2008),

Thesis title: “Efficient Algorithm and architecture for Implementation of Multiplier circuits in Modern FPGAs”.

· Wan Hoi Cheung (M.A.Sc. 2006), Co-Supervised with Dr. W. Lynch

Thesis title: “Low power design of Motion Compensation Module for MPEG Video Transcoder in DCT-Domain”

· Houman Zarrabi (M.A.Sc. 2006), Co-Supervised with Y. Savaria

“On the Design and Synthesis of Differential Clock Distribution Network”.

· Shaoqiang Bi, (M.A.Sc. 2004), Co- Supervised with DR. Wei Wang.

Thesis Title: "Low Power Modulo Reduction Technique and its Application in Residue-to-Binary Converters”.                                                                                                                                                    

· Shihong Deng (M.A.Sc.2004),

Thesis Title: Technology-Portable DSM CMOS Short Circuit Current Estimation                                                                                                                                                                                          

· WassimTout(M.A.Sc.2003).

Thesis Title: "Quantative Evaluation of the Impact of Floating Point Arithmetic Units on Performance of DSP Structures"

· Pedro Manrique, (M.A.Sc. 2002) co-supervision with Dr. B. Haroun
Thesis Title: "Software and Hardware Co-Design of Adaptive Digital Filters,"

· Qing Li, (M.A.Sc. 2002) Co-Supervising with Dr. M.R. Soleymani
Thesis Title: " Topic Architectures for Decoder-Encoder for Turbo Codes,"

· Wahidul Islam - M.A.Sc. 2002 in Elec. and Computer Engineering. (Co-supervised with Dr. K. Khorasani)
Thesis Title: “Stability of Haptic Displays in Distributed Virtual Environment”.

· S.Y. Shah, (M.A.Sc. 2000)
Thesis Title: " Low Power Floating Point Architectures for DSP,"

· C.Y. Pai, (M.A.Sc. 2000), co-supervision with Dr. B. Lynch
Thesis Title: "Data Dependent low power 8 x 8 DCT/IDCT,"

· Adnan Kabbani (M.A.Sc. 1999)
Thesis Title: "Modeling Noise Effects on Dynamic CMOS Circuits,"                                                                                                                                                    

· Amal Khailtash (M.A.Sc. 1999), co-supervision with Dr. B. Haroun.
Thesis Title: "Handling Large Data Storage in Synthesis of Multiplier FPGA Systems,"                                                                                                                              

· Jingyuan Sun (M.A.Sc. 1998)
Thesis Title: "Optimization of High Speed CMOS Circuits with Analytical Models for Signal Delay".

· Behzad Sajjadi (M.A.Sc. 1996), Co-supervised with Dr. B. Haroun
Thesis Title:"Architectural Synthesis for FPGA Based Signal Processing Systems".

· Haider Ahmed (M.A.Sc. 1995)
Thesis Title: "Design of a 2-D micromachined accelerometer".

· Fridge Rouatbi (M.A.Sc. 1992), Co-supervised with Dr. B. Haroun
Thesis Title: "Supply Current Simulation in CMOS Circuits".

· Jahangir Dewan (M.A.Sc. 1992), Co-supervised with Dr. B. Haroun
Thesis Title: "Performance Analysis and Design of Optimized Static Ram Access Memory".

· Niaz Khan (M.A.Sc. 1992), Co-supervised with Drs. R.V. Patel, N. Dimopolous
Thesis Title: "Depth Perception from Neural Network Based Approach for Automated Visual Inspection in VLSI Wafer Probing".

· Hala Table (M.A.Sc. 1990)
Thesis Title: "Design of a Fast Adder Accumulator".

· Zhu Yi (M.A.Sc. 1988)
Thesis Title: “Performance Analysis and Optimum Design of CMOS Buffers”.

· Khalid Ammar (M.A.Sc. 1988)
Thesis Title: “Design Rule Checking Package for CMOS”.

· K. Saleh (M.A.Sc. 1985)
Thesis Title: “Using a Single Chip Microcomputer as a Remote Interface Device in Fire Detection Systems”.

· Allan Brown (M.A.Sc. 1985)
Thesis Title: “Design of an Ultrasonic Flaw Detector Unit for Offshore Structures”.

Master of Engineering. (4 credit, 9 credit or 13 credit projects)

· Qi Nan Qi (2007)

Project Title: Design and Implementation of Parallel Prefix Incrementor/Decrementor.

· K.Vitoroulis (M.Eng. 2006)

Project Title: Automated Generation of Parallel Prefix Adders.

· Weige Chu (M.Eng. 2005)

Ptoject Title: Modulo-Reduced Residue to Binary Converter.

· Mohammad Masoud Shah (M.Eng. 2004)

· Ren Hong (M.Eng. 2004)

Project Title: Full Custom design of ANT-Based 8-bit Incrementor/Decrementor.

· Chen Kung Ching (M.Eng. 2004)

Project title: 64 bit Adders

· Sulei Ma (M.Eng. 2004)

Project Title: Implementation of Squarer for 32-bit Signed Numbers

· Ahmed Shehzad (M.Eng. 2004)

· Zheng Tong (2003)

Project Title: Comparison of Various Dynamic 8-bit Adders

· Jamshid Ourmazdi (M. Eng. 2003).

· Project Title “Design and Implementation of an Asynchronous Shift and Add Multiplier”.

· Haiqing Zhang (M. Eng. 2003)

· Project Title: Shift and Add Multiplier (Full Custom Design)

· Haiying Ji (M. Eng. 2003)

Project Title: Implementation, Simulation and Synthesis of 32-Bit Squarers

· Huang Zhengrong (M. Eng. 2003)

Project Title: Full Custom Design of 32-Bit Squarer

· Zhi Chen (M. Eng. 2003)

Project Title: Design of a General N-Bit Squarer

· Shao Xun Zhang (M. Eng. 2003) (together with Xu Feng Zhao)

Project Title: 8-Bit Full Adder using PDL, AII-N, and SFEG Dynamic Logic Style

· Xu Fang Zhao (M.Eng. 2003) (together with Shao Xun Zhang).

· Project Title: “8-bit Full Adder Design using PDL, AII-N, TSPC and SFEG Dynamic Logic Style”.

· Yun Jin (2003)

Project Title: “Design and Implementation of Dynamic 8-Bit Adders”

· Thesis title: Automation Tool for Generating VHDL Code of Scalable Squarer

· Li Zheng (M. Eng. 2002)

· Yangping Zhao (M.Eng. 2002)

· Yuhua Weng, (M.Eng. 2002)
Project Title: "A Scalable Floating Point adder generator Using C/C++ and VHDL ,"

· Shenggang Wang (M. Eng. 2002)
Project Title: "A Scalable Carry Look-Ahead Adder Generator,"

· M. FalakParvaz (M. Eng. 2002)
Project Title: "Division on radix-2 with restoring recurrence method,"

· N. Uz Zaman (M. Eng. 2001)
Project Title: "16 and 32 bit Constant Coefficient Multipliers- Pattern based Algorithm,"

· Yuan Zhang (M. Eng. 2002)

· Dong Xu (M.Eng. 2002)
Project Title: "Manchester Adder with Embedded VHDL in C Language,"

· Jian Mei Yang (M. Eng. 2002)
Project Title: "Scalable Carry Ripple Adder Generator,"

· Fan Jing (M. Eng. 2002)

· Shen Lei (M.Eng. 2002)
Project Title: "4 to 64 bits Array Multiplier VHDL Code Generator,"

· Xiaodong Wang (M. Eng. 2002)
Project Title: "Synthesis and Comparison of Various Adders,"

· Shailash Shah (M. Eng. 1999) [9 credit project]
Project Title: "Parallel Multiplier Design and Synthesis,"

· Shiva Kumar Musini (M.ENG. 1998) [9 credit]
Project Title: .Scalable & Synthesizable VHDL Coding of a Triple Data Path Floating Point Adder.

· Cong Xiao (M.ENG. 1998)[6 credit]
Project Title :The Designs of Four Multipliers and Comparison Between Them on Speed,Area and Power Consumption.

· W.Zhang (M.ENG. 1998)[3 credit]
Project Title:"A Tutorial of FPGA Behavioral & RTL Modelling,".

· Ahlam Nabbus (M.ENG. 1998) [3 credit]
Thesis Title:"A Tutorial on Synopsis, Behavioral Compiler,".

· Bogdan Staicu (M.ENG. 1998) [6 credit]
Project Title :"Automatic Characterization Technique for Cell Libraries,".

· M Sharma (M.ENG. 1997) [9 credit]
Project Title:"An Algorithm for Clock Network Distribution,".

· M. Moazzam (M.ENG. 1996) [9 credit]
Project Title :"Systolic Array Optimization Package,".

· K. Kechichian (M.ENG. 1994) [9 credit]
Project Title :"An Optimization Package for CMOS Circuits,".

· David Glen (M.ENG. 1992) [9 credit]
Co-supervised with Dr. D. Al-Khalili Thesis Title :"Analysis of Minimum Width Resistor in CMOS4B Process,".

· Vrionis (M.ENG. 1991) [9 credit]
Project Title :"The Optimizer A Software Package for CMOS Circuits Optimization,".

· H. Kekli (M.ENG. 1986) [9 credit]
Project Title: "Test Vector Generation for Combinational Circuits,".

· Ammar (M.ENG. 1986) [9 credit]
Project Title: "Comparison of Systolic and Non-Systolic Data Structures,".

Currently (Co-) Supervising the following Students:

§ Ali Valaee - M.A.Sc. in Electrical and Computer Engineering. Fall 2010 .

Department of ECE	People of ECE	Faculty of ECE	Asim Al-Khalili

You are visitor #
Last Modified on